Data-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with today's leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.