VLSI Circuits 2007
Conference paper

A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing

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Combinations of circuit techniques enabling tolerance to VT fluctuations in SRAM cell transistors during Read or Write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9Kb × 74b PDSOI CMOS SRAM array with a conventional 65nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58V and 0.40V/0.54V for single and dual VDD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.