A Pico-Joule Class, 1 GHz, 32 KByte × 64b DSP SRAM with Self Reverse Bias

Abstract

New SRAM circuit techniques implemented in a standard 0.13 μm bulk Si CMOS process are reported in this work that (i) enable pico-joule energy dissipation per accessed bit at 1 GHz, (ii) lower total leakage power by over 80% from all unaccessed cells, during both active and standby modes, using a rigorous, self reverse biasing scheme that addresses leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each and (iii) enable a programmable leakage reduction option that lowers leakage by over 90% when stored data is no longer desired.