Sungjae Lee, J. Johnson, et al.
VLSI Technology 2012
This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 urn SOI CMOS technology. An effective capacitance density of 1.76 fF/μm2 is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.
Sungjae Lee, J. Johnson, et al.
VLSI Technology 2012
A. Bette, J.K. DeBrosse, et al.
VLSI Circuits 2003
Jonghae Kim, Jean-Olivier Plouchart, et al.
IMS 2003
Jean-Olivier Plouchart, Noah Zamdmer, et al.
IEEE Transactions on Electron Devices