A Low-Capacitance Bipolar/BiCMOS Isolation Technology, Part II—Circuit Performance and Device Self-Heating

Abstract

Device and circuit results from transistors fabricated with a novel bipolar isolation technology are presented and discussed. The isolation structure, called sequentially planarized Interlevel isolation technology (SPIRIT), is fabricated by using a combination of selective epiaxial growth of silicon and a preferential polishing technique as the key process elements. This structural concept aims for reduced collector-substrate and collector-base capacitances, as well as a lower extrinsic base contact resistance, in a partial-SOI structure without significantly increasing the device temperature during operation. The feasibility of the isolation structure is demonstrated through ECL ring oscillators with gate delays of 23.6 ps at 0.72 mA and 47 ps at 0.23 mA. The temperature contours for SPIRIT and other bipolar isolation structures are simulated by using a finite-element method. It is shown that the capacitance versus self-heating tradeoff of SPIRIT is significantly improved over that of conventional trench or SOI isolation structures. © 1994 IEEE.