VLSI Technology 1990
Conference paper

A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices

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A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while keeping the CMOS devices at 3.3 V for reliable operation. With such a circuit, performance gain over CMOS is achieved at a reduced channel length and voltage. This demonstrates the feasibility of scaling BiCMOS technology to reduced channel length and power supply voltage. © 1990 IEEE.