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Publication
Nano-Net 2007
Conference paper
A 90nm CMOS Cryptographic Core with Improved Fault-Tolerance in Presence of Massive Defect Density
Abstract
This paper presents the development methodology, circuit realization and measurement of a cryptographic core intended to operate reliably in the presence of massive defect density. A circuit-level voter based on averaging and thresholding has been implemented, and is measured to offer superior reliability in comparison with standard techniques.