Alessandro Cevrero, Ilter Ozkaya, et al.
VLSI Circuits 2017
A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the gm/gds ratio of the current sources can be achieved. A power supply rejection of >22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80 pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.255 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7V and a clock frequency of 1.6 GHz. © 2006 IEEE.
Alessandro Cevrero, Ilter Ozkaya, et al.
VLSI Circuits 2017
Thomas Morf, Bernhard Klein, et al.
MEMS 2013
Thomas Toifl, Christian Menolfi, et al.
CSICS 2007
Christian Kromer, Gion Sialm, et al.
IEEE Journal of Solid-State Circuits