VLSI Technology 2003
Conference paper

A 0.18μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications


This paper discusses the fabrication of 2Kb array test chip with a 1.66μm2 cell and a corresponding 128Kb MRAM (Magnetoresistive Random Access Memory) with a 1.4 μm2 cell. The technology features a 1 transistor 1 MTJ (Magnetic Tunnel Junction) cell in a 0.18μm, 3 level Cu metallization logic-based process. Outlined here is a yield analysis of the read operation, which is governed by the MTJ resistance distribution function and a systematic study of the write operation. MRAM functionality, with a checkerboard disturb pattern, was obtained after process optimization. Write endurance tests did not show degradation of the cell properties.