ECTC 2011
Conference paper

3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections

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3D integration, using fine-pitch and high density vertical interconnects (TSVs), has been drawing considerable interest due to its promise for higher performance and smaller form factor. As the number of I/O increases and the pitch size decreases, interconnect joining process and reliability become critical in the assembly of 3D chip stacks. In this study, 3D chip stacks with more than 48,000 Pbfree solder micro-bump interconnects at 50 μm pitch were assembled and the joint reliability evaluated. Multiple bonding processes were developed, enhanced and characterized by investigating the influence of various bonding parameters such as atmosphere, compression mode and temperature profile on the joint formation. Various test vehicle sizes with multiple layers of thinned die were successfully assembled using the enhanced bonding profile. Underfilling of the narrow gaps between the stack dies was demonstrated using underfills with fine-particle fillers. The assembly yield and interconnection parasitic resistance was quantitatively studied as a function of the number of die layers. The reliability silicon die stacks integrated into modules with organic laminates was characterized by thermal cycling tests. © 2011 IEEE.