Characterization of stacked die using die-to-wafer integration for high yield and throughput

Abstract

We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-μm thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1 -die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume leadfree interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mΩ The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications. © 2008 IEEE.