MICRO 2022

1st Workshop on Data Integrity and Secure Cloud Computing (DISCC-2022)

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Recent papers from Meta (Facebook) and Google [1-3] have created a major concern about data integrity in large-scale computing in cloud data centers. The term “mercurial cores” has been coined [2] to refer to errant processor cores that have been clearly diagnosed as being the source of generating silent data errors – and recent panels (as referred to above) have brought together experts from cloud service providers and processor chip designers with the objective of raising awareness of this acute problem, and also encouraging leading edge research to devise affordable chip and system-level mitigation solutions. In addition to such data integrity concerns, the rise of data security and privacy breaches in cloud computing environments has accelerated research and development of practical solutions that enable computing with encrypted data (e.g., advanced cryptographic methods like Fully Homomorphic Computing or FHE); e.g., recent papers [4-6]. This workshop (DISCC-2022) proposes to bring together aspects of data integrity and security in a single, unified forum. The workshop will comprise a keynote speech, several contributed papers and, time permitting, a closing panel session involving leading edge experts in data integrity and security in a hyper-scale cloud computing setting. Potential speakers are encouraged to submit an extended abstract (1-2 pages) highlighting the key contributions in the light of the above-stated technical scope of the problem. Solution approaches at the algorithm, software/firmware and/or hardware level are encouraged for early dissemination and discussion in a workshop setting. Topics of interest include but are not limited to: Testing (including detection and/or diagnosis) of silent data errors (SDEs) for plaintext and/or HE-mode ciphertext computation. Detection and mitigation of malicious attacks that can lead to SDEs. Privacy-preserving data-secure computation: novel software and/or hardware solutions. Characterization of HE workloads for “discovery” of hardware acceleration primitives. Simulation and/or emulation based modeling methods to evaluate DISCC domain software-hardware solutions. Modeling of cloud-edge solutions for specific safety-, security- and/or privacy-critical applications: e.g., autonomous vehicles, internet banking, credit card fraud detection, etc. References H. D. Dixit, S. Pendharkar, M. Beadon, C. Mason, T. Chakravarthy, B. Muthiah, S. Sankar, “Silent data corruptions at scale,” , Feb. 22, 2021. P. H. Hochschild, R. Govindaraju, D. E. Culler, “Cores that don’t count,” HotOS ’21, May 31 – June 2, 2021, Ann Arbor MI. D. F. Bacon, “Detection and prevention of silent data corruption in an exabyte-scale database system,” The 18th IEEE Workshop on Silicon Errors in Logic – System Effects, IEEE (2022) N. Samardzic, A. Feldman, A. Krastev, N. Manohar, S. Devadas, K. Edefravy, C. Peikert, D. Sanchez, “CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data,” Proc. International Symp. on Computer Architecture (ISCA), June 2022. S. Kim, J. Kim, M. J. Kim, W. Jung, J. Kim, M. Rhu, J. H. Ahn, “BTS: An Accelerator for Bootstrappable Fully Homomorphic Encryption,” Proc. International Symp. on Computer Architecture (ISCA), June 2022. A. Feldmann, N. Samardzic, A. Krastev, S. Devadas, R. Dreslinski, K. Eldefrawy, N. Genise, C. Peikert, D. Sanchez, “F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version),” ; also appeared at MICRO, Oct. 2021.