Tenko Yamashita

Title

Senior Manager - Advanced Logic Pathfinding Technology

Bio

Tenko Yamashita is a principal research scientist and senior manager in the advanced logic pathfinding organization at IBM Research. He is currently leading the CMOS technology research for 1nm and beyond and driving the long-term CMOS transistor roadmap for IBM and for the joint research partners.

Since joined IBM research at Albany in 2009, Tenko has been working on FinFET, Nanosheet, VTFET and recently he is working on the 3D stacked transistors and the advanced interconnect technologies. He has received several Outstanding Technical Achievement Awards (OTAA), Research Division Awards (RDA) for his technical contributions to the early transistor technology developments. Tenko is the recipient of the IBM corporate award, The Best of IBM in 2019 for his contribution to FinFET technology research and IBM Z15 productization.

Tenko has authored or co-authored more than 45 papers in the major semiconductor conferences i.e. IEDM, VLSI Symposium etc and IEEE journals. Tenko is a member of IEEE and currently he is the ALT sub-committee member of IEDM from 2023.

Tenko graduated from Kyushu University, Fukuoka, Japan with a master's degree in physics in 1992.

Publications

Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures
- - Zuoguang Liu
  - Heng Wu
  - et al.
- 2019
- VLSI Technology 2019
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
- - Miaomiao Wang
  - Jingyun Zhang
  - et al.
- 2019
- IRPS 2019
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- - Heng Wu
  - Oleg Gluschenkov
  - et al.
- 2018
- IEDM 2018
Technique for Asymmetric Source/Drain Resistance Extraction on a Single Gate Length MOSFET
- - Phil Oldiges
  - Chen Zhang
  - et al.
- 2018
- SISPAD 2018
FinFET external resistance analysis by extended shift-and-ratio method
- - Chen Zhang
  - Zuoguang Liu
  - et al.
- 2018
- IEEE T-ED
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- - Chun Wing Yeung
  - Jingyun Zhang
  - et al.
- 2018
- IEDM 2018
Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology
- - S. Reboh
  - R. Coquand
  - et al.
- 2018
- Applied Physics Letters
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- - Heng Wu
  - Soon-Cheon Seo
  - et al.
- 2017
- IEDM 2017
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
- - Zuoguang Liu
  - Oleg Gluschenkov
  - et al.
- 2017
- VLSI Technology 2017
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- - N. Loubet
  - T.B. Hook
  - et al.
- 2017
- VLSI Technology 2017

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Patents

- 11 Sep 2023
- US
- 11756957
Reducing Gate Resistance In Stacked Vertical Transport Field Effect Transistors
- 11 Sep 2023
- US
- 11757012
Source And Drain Contact Cut Last Process To Enable Wrap-around-contact
- 28 Aug 2023
- US
- 11744065
Read-only Memory For Chip Security That Is Mosfet Process Compatible
- 27 Jul 2023
- CN
- ZL201880032182.7
Embedded Bottom Metal Contact Formed By A Self-aligned Contact Process For Vertical Transistors
- 19 Jun 2023
- CN
- ZL201880069329.X
Approach To High-k Dielectric Feature Uniformity
- 15 May 2023
- US
- 11652006
Finfet Complementary Metal-oxide-semiconductor (cmos) Devices
- 06 Feb 2023
- US
- 11575003
Creation Of Stress In The Channel Of A Nanosheet Transistor
- 30 Jan 2023
- US
- 11569229
Stacked Vertical Transport Field Effect Transistors With Anchors
- 25 Jan 2023
- JP
- 7217579
H-shaped Vfet With Increased Current Drivability
- 23 Jan 2023
- US
- 11562906
Low Resistance Source Drain Contact Formation With Trench Metastable Alloys And Laser Annealing

Top collaborators

Tenko Yamashita

Title

Bio

Publications

Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures

Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor

Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm

Technique for Asymmetric Source/Drain Resistance Extraction on a Single Gate Length MOSFET

FinFET external resistance analysis by extended shift-and-ratio method

Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Integrated dual SPE processes with low contact resistivity for future CMOS technologies

Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

Patents

Reducing Gate Resistance In Stacked Vertical Transport Field Effect Transistors

Source And Drain Contact Cut Last Process To Enable Wrap-around-contact

Read-only Memory For Chip Security That Is Mosfet Process Compatible

Embedded Bottom Metal Contact Formed By A Self-aligned Contact Process For Vertical Transistors

Approach To High-k Dielectric Feature Uniformity

Finfet Complementary Metal-oxide-semiconductor (cmos) Devices

Creation Of Stress In The Channel Of A Nanosheet Transistor

Stacked Vertical Transport Field Effect Transistors With Anchors

H-shaped Vfet With Increased Current Drivability

Low Resistance Source Drain Contact Formation With Trench Metastable Alloys And Laser Annealing

Top collaborators

Dechao Guo

Huiming Bu

Dan J. Dechene

Nicolas Loubet