SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural NetworksSanchari SenShubham Jainet al.2019IEEE TC
A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation KernelEri OgawaKazuaki Ishizakiet al.2019COOL CHIPS 2019
Data Subsetting: A Data-Centric Approach to Approximate ComputingYounghoon KimSwagath Venkataramaniet al.2019DATE 2019
A Scalable Multi-TeraOPS Core for AI Training and InferenceSunil ShuklaBruce Fleischeret al.2018IEEE SSC-L
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and InferenceBruce FleischerSunil Shuklaet al.2018VLSI Circuits 2018
DyHard-DNN: Even more DNN acceleration with dynamic hardware reconfigurationMateja PuticAlper Buyuktosunogluet al.2018DAC 2018
Compensated-DNN: Energy efficient low-precision deep neural networks by compensating quantization errorsShubham JainSwagath Venkataramaniet al.2018DAC 2018
Exploiting approximate computing for deep learning accelerationChia-Yu ChenJungwook Choiet al.2018DATE 2018
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory AcceleratorsSwagath VenkataramaniJungwook Choiet al.2017PACT 2017
Low-overhead Error Prediction And Preemption In Deep Neural Network Using Apriori Network Statistics24 May 2021US11016840
Programmable Data Delivery By Load And Store Agents On A Processing Chip Interfacing With On-chip Memory Components And Directing Data To External Memory Components16 Nov 2020US10838868
Processor And Memory Transparent Convolutional Lowering And Auto Zero Padding For Deep Neural Network Implementations17 Feb 2020US10565285
MOMori OharaDeputy Director, IBM Research Tokyo, Distinguished Engineer, Chief SW Engineer for Hybrid Cloud on IBM HW