Swagath Venkataramani

Title

Principal Research Scientist, AIU Architecture and Compilers

Publications

MixTrain: accelerating DNN training via input mixing
- - Sarada Krithivasan
  - Sanchari Sen
  - et al.
- 2024
- Frontiers in Artificial Intelligence
A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC
- - Monodeep Kar
  - Joel Silberman
  - et al.
- 2024
- ISSCC 2024
DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU
- - Sanchari Sen
  - Shubham Jain
  - et al.
- 2024
- IEEE Micro
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- - Monodeep Kar
  - Joel Silberman
  - et al.
- 2024
- IEEE Journal of Solid-State Circuits
Deep Compression of Pre-trained Transformer Models
- - Naigang Wang
  - Chi-Chun Liu
  - et al.
- 2022
- NeurIPS 2022
Approximate computing and the efficient machine learning expedition
- - Jörg Henkel
  - Hai Li
  - et al.
- 2022
- ICCAD 2022
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators
- - Subhankar Pal
  - Swagath Venkataramani
  - et al.
- 2022
- Transactions on Embedded Computing Systems
Accelerating Inference and Language Model Fusion of Recurrent Neural Network Transducers via End-to-End 4-bit Quantization
- - Andrea Fasoli
  - Chia-Yu Chen
  - et al.
- 2022
- INTERSPEECH 2022
Accelerating DNN Training Through Selective Localized Learning
- - Sarada Krithivasan
  - Sanchari Sen
  - et al.
- 2022
- Frontiers in Neuroscience
A 7-nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
- - Sae Kyu Lee
  - Ankur Agrawal
  - et al.
- 2021
- IEEE JSSC

Patents

- 25 Feb 2025
- ES
- 4356236
Reformatting Of Tensors To Provide Sub-tensors
- 25 Feb 2025
- IE
- 4356236
Reformatting Of Tensors To Provide Sub-tensors
- 24 Feb 2025
- US
- 12236338
Single Function To Perform Combined Matrix Multiplication And Bias Add Operations
- 11 Nov 2024
- US
- 12141513
Method To Map Convolutional Layers Of Deep Neural Network On A Plurality Of Processing Elements With Simd Execution Units, Private Memories, And Connected As A 2d Systolic Processor Array
- 15 Oct 2024
- GB
- 2604060
Hybrid Data-model Parallelism For Efficient Deep Learning
- 16 Sep 2024
- US
- 12094525
Multichannel Memory To Augment Local Memory
- 05 Aug 2024
- US
- 12056594
Low Precision Deep Neural Network Enabled By Compensation Instructions
- 08 Jul 2024
- CN
- ZL201980032566.3
Low Precision Deep Neural Network Enabled By Compensation Instructions
- 02 Jun 2024
- JP
- 7497946
Hybrid Data-model Parallelism For Efficient Deep Learning
- 30 Apr 2024
- TW
- I840790
Single Function To Perform Combined Matrix Multiplication And Bias Add Operations

Top collaborators

Matthew Ziegler

Principal Research Scientist

Alberto Mannari

Software Developer

Xiaodong Cui

Principal Research Scientist

Kaoutar El Maghraoui

Principal Research Scientist and Manager, AIU Spyre Model Enablement, AI Hardware Center