Bio
Lane Meyer has been a mainstay on IBM's Industrial Engineering (IE) team at the Albany NanoTech semiconductor R&D facility since 2019. He interned at GlobalFoundries Fab 8 in 2017 and at IBM Research in 2018. Shortly after, he graduated from Rensselaer Polytechnic Institute (RPI) with a degree in Industrial and Management Engineering (IME). In his role supporting Fab Operations, Lane has been involved in numerous projects onsite.
Most notably was planning and tracking the world's first hardware demonstration of a chip with 2 nanometer technology in 2021. This feat in logic scaling called a nanosheet has been further developed through the Rapidus partnership in which Lane is an expert in creating detailed production plans called waterfalls. These forecasts require auditing the raw process time (RPT) for thousands of individual steps in the manufacturing flow, factoring in design of experiments called splits, tracking upcoming scheduled tool downtime, and collaborating with researchers on additional engineering needs. Lane has taken the lead on preparation and communication for IBM's Rocket Lots, the highest priority wafers with the most aggressive cycle time expectations. Past Rocket Lot efforts have expedited critical nanosheet cycles of learning and device verification milestones.
In addition to logic scaling, Lane has been the lead IE rep for IBM's Chiplet and Advanced Packaging program at Albany NanoTech. A chiplet is a packaged system of sub-elements such as a computational processor, graphics, memory, AI accelerator, I/O function, or a host of other chip functions. There is added complexity for Fab Operations as it requires hybrid wafer-to-wafer bonding, far-BEOL specific tooling, and its own designated C4 manufacturing space. During the C4 line install, he helped establish its unique operation procedures and has since been monitoring its key performance metrics.
Industrial Engineering is delegated not just across research programs but also tooling sectors. While Lane has covered most of the sectors onsite, his current concentration is lithography (LTH) and wet cleaning processes (WET). His responsibilities include short and long-term capacity sizing, analyzing tool performance data, and leading continuous improvement projects. Recently, Lane has spearheaded innovating a new way of real time dispatching (RTD) for a high-volume WET tool that improves the operators' ability to maximize parallel processing, distribute jobs across alternate tools, and increase throughput at this pinch point.
Behind the scenes, Lane has also created and maintained the site-wide Productivity Target Model. By analyzing over a million rows of tool classification, utilization, and production data, the team can calculate daily productivity benchmarks. This was instrumental in defining the roadmap for increasing IBM productivity by 25% since 2023.