Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures
- IEEE Computer Architecture Letters
I'm a research staff member in the Hybrid Cloud Research department of the IBM Zurich Research Laboratory (Switzerland), which I joined in 1997.
My area of research is high-speed networking, with an emphasis on architecture and VLSI design of server interconnect fabrics and accelerators for computer interconnection networks. I received a Dipl.-Eng. degree from the Ecole Nationale d’Ingénieurs (now UTBM), Belfort, France, and a Master's in microelectronics from the Institut Supérieur de Microélectronique Appliquée (now EMSE-ISMIN), Marseille, France.
What keeps me busy ?
I am currently working on a disaggregated cloud and computing infrastructure for FPGAs. The goal of this project is to deploy FPGAs at large scale in hyperscale data centers.
Previous research projects
Cloud and computing infrastructures
[2016-Now] cloudFPGA - Field programmable gate arrays for the cloud
[2014-2015] Enabling FPGAs in Hyperscale Data Centers
Hardware accelerator techniques and their applications
[2008-2013] Rx Stack Accelerator for 10 GbE Integrated NIC
Optical Packet Switching
[2004-2007] The OSMOSIS research project
High-Speed Packet Switching ASICs
[2000-03] Prizma-DPRS Switch Architecture
[1999-00] Prizma-EP Switch Chip (IBM PowerPRS 64G)
[1998-99] Network Processor Load Balancing for High-Speed Links
[1997-98] Prizma-E Switch Chip (IBM PowerPRS 28G)
Before joining IBM in 1997, I was a hardware engineer at Telmat Informatique, where I designed architectures and electronic boards for Unix multiprocessor servers and Transputer-based parallel supercomputers.
During that period I participated in several European projects in which I conducted research in the fields of real-time 3-D graphics (The Spirit Workstation) and Transputer-based networking (Supernode).