What is chip packaging?

If you’ve ever read anything about semiconductors, you’ve probably seen a photo of someone holding up a wafer. They’re silicon disks containing hundreds of future computer chips. But you can’t just cut up those semiconductor chips and plug them into a circuit board. They need to be packaged up in materials that keep them safe, reliable, and allow electricity to efficiently flow through them. “It’s how the chip communicates with the rest of the world,” said Dale McHerron, IBM’s chief strategist for chiplets and advanced packaging research. This process of packaging the chips results in a chip module.

As computer chips have continued to shrink over the years, more research is required to continue packaging them up as efficiently as possible. There are two overarching areas of research in packaging — the materials used to house the chips, and how those materials are processed to build complete chip modules. Let’s break them down.

Chip packaging materials research

In a nutshell, chip packaging provides the mechanical environment where a computer chip operates. The packaging gives the chip power and accommodates the input and outputs that allow it to communicate with the rest of the compute system. Chips also tend to get hot when they run, so the packaging aims to maintain a certain temperature range so that the chip doesn’t overheat.

Many modern microelectronic modules are built around roughly the same materials, called organic substrates, after decades of trial and error across the industry. The core material for most is a material called FR-4, which is made up of woven fiberglass and an epoxy resin — which also happens to be flame-resistant. The FR-4 panel is often laminated with a thin layer of copper foil, a highly conductive material. Research is underway looking into other materials for chip packaging, such as cores made from glass, which could allow for much faster data transfers and smaller chip structures. But this work is still likely years out from production.

On top of the laminate are layers built up for the copper wiring in the package. The A dielectric is an insulating material that when polarized, don't low electric current to flow through them.dielectric build-up layers between are made by a single company called Ajinomoto, which is primarily known for food packaging. It turns out that packaging up tasty treats isn’t too different a process from making the layers needed in an organic laminate — at least from a chemistry perspective. But we wouldn’t recommend eating these laminates.

The base substrate material is generally standardized for chip packaging across a lot of different applications. And for situations where a chip has to operate in very warm situations, it’s more about how the devices are cooled, rather than the materials used in its laminate construction. And that’s handled on the back side of the chip.

The chip is attached to the organic substrate with solder balls called controlled-collapse chip connections, or C4s — which IBM actually invented decades ago. Then, a liquid epoxy underfill material is used to isolate the balls. As chips continue to shrink in size, we need to find new ways of connecting parts together, as the solder currently used in the C4 balls can’t effectively shrink as well as other parts of the chip. IBM is pioneering new methods, such as hybrid bonding, where layers of copper and an oxide dielectric are used to bind chips directly together with no intermediary solder connection.

When scaling down chips, you need to ensure all the components have an extremely high level of reliability, because there’s little room for failure. Stresses on the various structures can change as they get smaller. And with new advances in AI computing and new forms of chip designs, there is a renewed need for a greater number of smaller interconnections between chips to support powerful AI training and inferencing models.

Much of the focus at IBM’s Albany NanoTech Complex facilities for packaging research now revolves around increasing the reliability and decreasing the dimensions of the copper wires and dielectric thickness needed to make high density interconnections between chips. New process technologies are being researched to design, build, and test components at these smaller dimensions. That includes stress-testing devices, and ensuring they can produce the signal strength and current needed in every potential operating situation. Parts undergo thermal cycling, assuring they can work in varying levels of temperature and humidity, as well as testing that mimics the entire lifespan of a module in a few weeks.

Chiplet packaging research

Beyond traditional chip structures, IBM Research is also investigating new ways to bring the power of AI and other cutting-edge modalities to life. One of the key challenges in the world of semiconductors is how to break apart the various functions of a system-on-a-chip into devices that can be configured to best solve a problem. These devices, called chiplets, could unlock powerful new capabilities, such as AI devices that stack together AI accelerators with several memory chiplets and a single input-output device, creating a chiplet set that could be used for inference of the most advanced AI models available.

Chiplets are a large area of focus for IBM’s semiconductor research, and how they’re effectively packaged is a large part of that work. Right now, there’s no standardization for how chiplets made by other companies would interact with each other, although there are proposals that various groups have backed. IBM is researching the ways that these devices could work, including designing high-bandwidth interconnects, how to stack silicon chips on top of each other, how the devices can all stay cooled, and how they all can maintain sufficient power in their packages. “We’re just starting to scratch the surface here,” said McHerron.

And it’s just the beginning of the packaging research revolution. “When CMOS scaling was in its prime, you didn’t need all this fancy packaging — all the innovations were happening in the silicon,” McHerron said. “Now the pendulum is swinging back from CMOS scaling innovations to packaging innovations where you’re packaging more silicon chips in a given space instead of just packing more transistors on a silicon chip through transistor scaling.”

System performance improvements can be made, with enhancements made in the way silicon and packaging technologies commingle, McHerron said. “We’re in a new era in packaging performance.”

Manufacturing process research

Once new semiconductors are designed and they’ve been tested in their packages, they need to be produced at scale. Research and testing also needs to be done here to ensure that the designs that work in the lab are easily producible at the scale the customers need them to be. This is part of the work that happens at IBM’s facility in Bromont in southern Quebec, Canada.

At Bromont, module packaging and testing is produced for a wide range of clients, including IBM —Bromont packages the chips in IBM Z and P systems. It also happens to be the largest Outsourced Semiconductor Assembly and Test (OSAT) facility in North America, and a US government-trusted facility. “Bromont is very much the D in R&D for chips at IBM,” said Etienne Lemieux, who manages R&D and business development at Bromont.

There are several ways that someone might come to work with the researchers and production staff at Bromont. In some cases, clients may come with an idea of how they want their chips to be packaged, and will ask the Bromont team to build prototypes and figure out the processes for manufacturing them at scale. Sometimes, clients come with a full design already in hand, but look to IBM’s production experience to make it more manufacturable. It’s rare that a client would come with a completely blank slate and look to IBM to design something from scratch, but it can happen. In most cases, however, the work is usually focused around trying to make chip packaging production more cost effective.

For most engagements, the entire process — from reaching out to IBM to delivering chips at scale — can take between six months and two years. Over that time, engineers and technicians will work to build manufacturing processes that make the most sense for the design they’re working with, delivering prototypes to the customer and getting feedback to iteratively reach the final output. Lemieux said it can take three to four iterations before all parties are happy with the processes’ reliability and cost efficacy.

Once the production-ready process and design are finalized, IBM will usually send them to the customer who will then rely on a manufacturer that can mount them on a card, like a PCIe card or a motherboard, depending on how they will be used.

When it comes to developing the chip packaging processes, the Bromont team does much of their work at Centre de Collaboration MiQro Innovation (C2MI), an advanced semiconductor research and development facility owned by the University of Sherbrooke, just down the road from the Bromont site. The C2MI site has roughly the same tooling as IBM within its Bromont facility, which allows the team to test ideas and then to bring them efficiently to the production line.

Much like the materials and architecture testing done in Albany, the Bromont team also stress test their processes to ensure they can produce the packaged chips with a high level of reliability. At C2MI, IBMers can test various thermal materials, parts assemblies, and underfills for their reliability during the production cycle. There are also stress tests for these processes, such as running their ideas through humidity chambers, and running a chip and process through heat changes from 0°C to 120°C over 200 times to ensure they’re robust enough for real-world use.

And similar to Albany, the team in Bromont have seen that packaging is now playing a much greater role in chip design and performance, and have worked to create processes where chips and their packages are far more interwoven than they were in recent years. “Packaging has become a much heavier ingredient in the performance of the overall module,” Lemieux said.