Keunwoo Kim, Rajiv V. Joshi, et al.
Solid-State Electronics
Paper
Optimal design of triple-gate devices for high-performance and low-power applications
Abstract
Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical n+}/p+ polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented. © 2008 IEEE.
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