Keunwoo Kim, Ching-Te Chuang, et al.
IEEE Transactions on Electron Devices
Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical n+}/p+ polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented. © 2008 IEEE.
Keunwoo Kim, Ching-Te Chuang, et al.
IEEE Transactions on Electron Devices
Hung Ngo, Keunwoo Kim, et al.
VLSI-TSA 2006
Rajiv V. Joshi, Keunwoo Kim, et al.
IEEE Transactions on VLSI Systems
Keunwoo Kim, R.V. Joshi, et al.
ISLPED 2003