Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
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31 results for Sean Burns
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
Speeding up OPC by leveraging existing designs with machine learning
- Cheng Chi
- Julian Dolby
- et al.
- 2021
- SPIE Advanced Lithography 2021
Electrical study of DSA shrink process and CD rectification effect at sub-60nm using EUV test vehicle
- Cheng Chi
- Chi Chun Liu
- et al.
- 2017
- SPIE Advanced Lithography 2017
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
Lithographic qualification of high-Transmission mask blank for 10nm node and beyond
- Yongan Xu
- Tom Faure
- et al.
- 2016
- SPIE Advanced Lithography 2016
DSA patterning options for FinFET formation at 7nm node
- Chi Chun Liu
- Elliott Franke
- et al.
- 2016
- SPIE Advanced Lithography 2016
Fin formation using graphoepitaxy DSA for FinFET device fabrication
- Chi Chun Liu
- Fee Li Lie
- et al.
- 2015
- SPIE Advanced Lithography 2015
10nm FINFET technology for low power and high performance applications
- D. Guo
- H. Shang
- et al.
- 2014
- ICSICT 2014
64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme
- Shyng-Tsong Chen
- Hideyuki Tomizawa
- et al.
- 2011
- IITC/MAM 2011