Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts
- Xiaoxiong Gu
- Joel Silberman
- et al.
- 2012
- EPEPS 2012
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28 results for Joel Silberman
A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor
- Shivakumar Swaminathan
- Sanjay B. Patel
- et al.
- 2005
- ISQED 2005
The circuits and physical design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- VLSI Circuits 2005
The circuit design of the synergistic processor element of a CELL processor
- O. Takahashi
- R. Cook
- et al.
- 2005
- ICCAD 2005
High-speed, power-conscious circuit design techniques for high-performance computing
- O. Takahashi
- S. Dhong
- et al.
- 2001
- VLSI-TSA 2001
1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache
- Joel Silberman
- Naoaki Aoki
- et al.
- 2000
- VLSI Circuits 2000
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor
- D. Heidel
- S. Dhong
- et al.
- 1998
- VTS 1998
690ps read-access latency register file for a GHz integer microprocessor
- O. Takahashi
- Joel Silberman
- et al.
- 1998
- ICCD 1998