Publications

59 results for Katsuyuki Sakuma

Vacuum ultraviolet (VUV) surface treatment process for flip chip and 3-D interconnections
- - K. Sakuma
  - N. Nagai
  - et al.
- 2009
- ECTC 2009
Simplified 20-μm pitch vertical interconnection process for 3D chip stacking
- - Katsuyuki Sakuma
  - Noriyasu Nagai
  - et al.
- 2009
- IEEJ Transactions on Electrical and Electronic Engineering
Characterization of stacked die using die-to-wafer integration for high yield and throughput
- - K. Sakuma
  - P. Andry
  - et al.
- 2008
- ECTC 2008
3D silicon integration
- - J. Knickerbocker
  - P. Andry
  - et al.
- 2008
- ECTC 2008
3D chip-stacking technology with through-silicon vias and low-volume lead free interconnections
- - Katsuyuki Sakuma
  - Paul S. Andry
  - et al.
- 2008
- IBM J. Res. Dev
3D chip stacking with C4 technology
- - Bing Dang
  - Steven L. Wright
  - et al.
- 2008
- IBM J. Res. Dev
Three-dimensional silicon integration
- - John U. Knickerbocker
  - Paul S. Andry
  - et al.
- 2008
- IBM J. Res. Dev
3D chip stacking technology with low-volume lead-free interconnections
- - K. Sakuma
  - P. Andry
  - et al.
- 2007
- ECTC 2007
Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package
- - B. Dang
  - S.L. Wright
  - et al.
- 2007
- ECTC 2007