William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 μm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ. Copyright 2008 by International Business Machines Corporation.
William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
Rolf Clauberg
IBM J. Res. Dev
Beomseok Nam, Henrique Andrade, et al.
ACM/IEEE SC 2006
Yigal Hoffner, Simon Field, et al.
EDOC 2004