Volume-controllable Solder Bumping Technology to Package Substrate Using Injection Molded Solder for Fine-pitch Flip ChipToyohiro AokiKatsuyuki Sakumaet al.2023ECTC 2023
Artificial Intelligence (AI) based methodology to minimize asymmetric bare substrate warpageSathya RaghavanHiroyuki Moriet al.2023ECTC 2023
Fabrication and Performance of 300-mm Wafer-Scale Silicon Microchannel CoolerEvan G. ColganKai Schleupenet al.2023IEEE Transactions on CPMT
Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked ModulesMukta FarooqArvind Kumaret al.2022ECTC 2022
Surface Energy Characterization for Die-Level Cu Hybrid BondingKatsuyuki SakumaRoy Yuet al.2022ECTC 2022
Thermo-mechanical Analysis of Thermal Compression Bonding Chip-Join ProcessPrabudhya Roy ChowdhuryKatsuyuki Sakumaet al.2022ECTC 2022
3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um Mixed Pitch Interconnections on High Density Laminate Katsuyuki SakumaMukta Farooqet al.2021ECTC 2021
Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer Dicing Technologies for 3D Heterogeneous IntegrationKatsuyuki SakumaDishit Parekhet al.2021ECTC 2021
3-D Die Stacking with 55 μm Pitch Interconnections on Advanced Ground-Rule Laminate for Artificial Intelligence SystemKatsuyuki SakumaMukta Farooqet al.2021IEEE Transactions on CPMT
Back to Finger-Writing: Fingertip Writing Technology Based on Pressure SensingGaddi BlumrosenKatsuyuki Sakumaet al.2020IEEE Access