In this study, the heterogeneous integration of three chips including an FPGA, HBM, and IBM AI chip on an organic interposer substrate using Cu-pillar micro-bump solder joint is investigated. The largest chip is the FPGA with a size of approximately 29 mm × 12 mm and containing more than 188,000 pads at 40 μm pitch. The organic substrate used in this study is 55 mm × 55 mm square with 4+1 7-2-7 layers and ENEPIG (electroless Ni/Pd/Au) surface finished pads. 2 μm/2 μm line and space RDL was used on the build-up substrate to achieve high-bandwidth interconnection between the FPGA and HBM. Belt-furnace reflow and normal thermo-compression bonding (TCB) processes could not connect the fine-pitch micro- bumps of large FPGA die without non-wet or solder bridging defects due to warpage and CTE differences. Therefore, to solve these issues, we have developed a new solder deposition technique that uses IMS (injection molded solder) to form a specified volume of solder in the right place on the organic interposer substrate. This advanced IMS process varied the solder amount across the die site to decrease volume in areas prone to bridging and increase volume in areas prone to non- wetting. The underfill process was also optimized to reenforce the package and reduce the stress from the substrate warpage and CTE mismatch. Selective cross-sectional analysis was used to study the geometry of micro-bumps after the chip join, and confirmed the micro-bumps were joined without defects. The results of the electrical measurement test after assembly confirmed that no short circuit has occurred.