Publication
ECTC 2021
Conference paper

3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um Mixed Pitch Interconnections on High Density Laminate

Abstract

The overall system performance of artificial intelligence (AI) hardware can be improved by using 3D integration technology which addresses the bottlenecks of accelerator-memory bandwidth and of accelerator-accelerator bandwidth. 3D integration using through-silicon-vias (TSV) and micro-bumps has benefits such as packaging density and high bandwidth due to the short connection lengths [1-3]. However, the warpage increases significantly as the die is made thinner, and hence reduces the reliability of the connection between the die and the organic laminate. In addition, differences in the coefficient of thermal expansion (CTE) mismatch between thin TSV die and organic laminate results in large amounts of mechanical stress on the connection during the bonding process [4]. This influence becomes more significant when the FC (flip chip) pad size and pitch on the laminate decreases. Therefore, there is an increased demand to develop and implement new chip joining methods that minimize 3D assembly yield issues. In this work, a 3D Die-Stack on Substrate (3D-DSS) bonding process has been developed to demonstrate a 3D die stack that has joined to a mixed pitch (55 μm / 75 μm) high density interconnect laminate. By using the 3D-DSS process with thermal compression bonding, the thin bottom die with TSVs can be bonded to a thick top die by being held flat by vacuum. This study used a semiconductor die that consisted of mixed pitch (55 μm / 75 μm) Cu pillars with a SnAg solder cap. Thin silicon dies have corresponding mixed pitch (55 μm / 75 μm) Cu-filled-TSVs and micro-bumps. The dimension of the high-density laminate was 35 mm ï‚´ 35 mm and it has 4+4 with additional build up layers. The thin film layers are directly integrated to one side of a conventional substrate. A selective cross-sectional analysis was used to study the geometry of the micro-bump connections after forming the 3D chip stack on the advanced ground rule laminate. The analysis confirmed that solder joints along the perimeter of chips were joined with full wetting and no bridging. Non-destructive X-ray images also confirmed there was no micro-bump bridging across the full chip area. The results of the experiment showed that 3D-DSS process can effectively prevent micro-bump bridging in a 3D die stack on a high-density laminate configuration. The modeling activities described in the present work is to screen the possible failure mechanism before the actual hardware are built. Parametric sweep is conducted for potential risks identification as well as design optimization. The modeling process begins with a package level model which accounts for the major structural components including the multiple chip carrier, the interposer, processor chip and HBM dies, and a metal lid serves both as mechanical protection and heat spreader. The interfaces among the components are appropriately simulated. In this step packaging stresses are reported at global level and compared against the known material limit. A major challenge for this technology lies in the interconnection reliability. To address that, sub-modeling of the interconnects will be illustrated. The stresses in solder micro-bump, back-end-of-the-line (BEOL) and the vias in the wiring board will be presented. How the local features impact on the interconnection reliability will be discussed. Acknowledgements: Griselda Bonilla, Russell Kastberg, Brian Quinlan, Brian Erwin, Buck Webb, Peter Sorce, Sankeerth Rajalingam, Yang Liu, Jae-Woong Nah Key words: AI hardware, 3D integration, fine pitch organic laminate, thermo-compression bonding, warpage, SnAg solder bump, FEM 1. J. U. Knickerbocker, et al., IBM J. Res. & Dev., vol. 52, 2008. 2. M.G. Farooq, et al., IEDM, 2011. 3. M.G. Farooq, et al., IRPS, 2015. 4. K. Sakuma et al., ECTC, pp. 647-654, 2014.

Date

01 Jul 2021

Publication

ECTC 2021

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