Publications

38 results for Victor Chan

Gate-induced-drain-leakage current in 45-nm CMOS technology
- - Xiaohin Yuan
  - Jae-Eun Park
  - et al.
- 2008
- IEEE T-DMR
Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology
- - Xiaobin Yuan
  - Jae-Eun Park
  - et al.
- 2007
- IIRW 2007
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- - Z. Luo
  - N. Rovedo
  - et al.
- 2007
- VLSI Technology 2007
Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates
- - Haizhou Yin
  - Z. Ren
  - et al.
- 2006
- ICSICT 2006
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- - Haizhou Yin
  - Z. Ren
  - et al.
- 2006
- VLSI Technology 2006
Direct silicon bonded (DSB) substrate solid phase epitaxy (SPE) integration scheme study for high performance bulk CMOS
- - Haizhou Yin
  - C.Y. Sung
  - et al.
- 2006
- IEDM 2006
Process induced stress for CMOS performance improvement
- - S. Fang
  - S.S. Tan
  - et al.
- 2006
- ICSICT 2006
Transistor scaling with novel materials
- - Meikei Ieong
  - Vijay Narayanan
  - et al.
- 2006
- Materials Today
Hybrid-orientation technology (HOT): Opportunities and challenges
- - Min Yang
  - Victor W.C. Chan
  - et al.
- 2006
- IEEE Transactions on Electron Devices
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- - Chun-Yung Sung
  - Haizhou Yin
  - et al.
- 2005
- IEDM 2005