Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates

Abstract

Various local stress techniques have been integrated on strainedSi directly on insulator (SSDOI) substrates, including dual stress liner (DSL), stress memory technique (SMT), and embedded SiGe (eSiGe) in source/drain. SMT shows mild drive current enhancement on nFETs. PFETs with eSiGe exhibit significant enhancement, suggesting eSiGe compatibility with SSDOI is excellent. A ring oscillator delay of 3ps is achieved at leakage current of 1μA/um and V DD=1.1V. © 2006 IEEE.