High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Conference paper
Publications
39 results for Dureseti Chidambarrao
Study of silicon strain in shallow trench isolation
- M. Belyansky
- N. Klymko
- et al.
- 2010
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
PaperReduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
Conference paper(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Conference paperStress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Conference paperEffect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
PaperDual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Conference paperIntegration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
- M. Horstmann
- A. Wei
- et al.
- 2005
- IEDM 2005
Conference paperHigh performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Conference paperDesign of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
Conference paper