IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area and Reliability
- David Wolpert
- Gerry Strevig
- et al.
- 2025
- ISSCC 2025
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36 results for Dureseti Chidambarrao
Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology
- Justin Zhu
- Katsunori Onishi
- et al.
- 2024
- IEEE MDTS 2024
Cores, Cache, Content, and Characterization: IBM’s Second Generation 14-nm Product, z15
- David Wolpert
- Chris Berry
- et al.
- 2020
- IEEE JSSC
IBM z15: Physical design improvements to significantly increase content in the same technology
- Christopher Berry
- David Wolpert
- et al.
- 2020
- IBM J. Res. Dev
IBM z15: A 12-Core 5.2GHz Microprocessor
- Christopher Berry
- Brian Bell
- et al.
- 2020
- ISSCC 2020
IBM z14: Processor characterization and power management for high-reliability mainframe systems
- Christopher Berry
- David Wolpert
- et al.
- 2019
- IEEE JSSC
Identification and sensitivity analysis of a correlated ground rule system (design arc)
- Eric Eastman
- Dureseti Chidambarrao
- et al.
- 2017
- SPIE Advanced Lithography 2017
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Study of silicon strain in shallow trench isolation
- M. Belyansky
- N. Klymko
- et al.
- 2010
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009