Publications

147 results for Thomas Morf

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2017
- IEEE JSSC
DDR4 transmitter with ac-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS Technology
- - Marcel Kossel
  - Christian Menolfi
  - et al.
- 2017
- ESSCIRC 2017
Background calibration using noisy reference ADC for a 12b 600MS/s 2×TI SAR ADC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- ESSCIRC 2017
VCSEL-based optical links in burst-mode slow optical power ramp-up and how to achieve ultra-short wake-up times
- - Thomas Morf
  - Marc Seifried
  - et al.
- 2017
- Electronics Letters
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
- - Elisa Sacco
  - Pier Andrea Francese
  - et al.
- 2017
- VLSI Circuits 2017
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- VLSI Circuits 2017
A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- VLSI Circuits 2017
Three-dimensional monolithic integration of III-V and Si(Ge) FETs for hybrid CMOS and beyond
- - Veeresh Deshpande
  - Vladimir Djara
  - et al.
- 2017
- Japanese Journal of Applied Physics
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- ISSCC 2017
A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2017
- ISSCC 2017