Xiaoxiong Gu, Joel Silberman, et al.
EPEPS 2012
A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key features and considerations of the proposed architecture are described. A proof-of-concept 16 lane, 16 Gb/s per lane source-synchronous I/O test chip was designed and fabricated in a 32 nm SOI CMOS technology. Several circuit techniques employed in the design of this test chip are described. These include a phase rotator based on current-integrating phase interpolator cores with architecture and circuit improvements to performance as compared to prior art, an active-inductor-based RX CTLE, and an 8:1 TX serializer with 8-phase clocking. Measurements demonstrate the operation of the test chip over ultra-short-reach channels with up to 10 dB of loss with greater than 30% timing margin. The I/O circuitry operates from 1 V supplies and achieves a power efficiency of better than 2 pJ/bit, making the proposed architecture suitable for use in high-density interconnect applications required for high-performance computing systems.
Xiaoxiong Gu, Joel Silberman, et al.
EPEPS 2012
Ankur Agrawal, Pavan Kumar Hanumolu, et al.
CICC 2011
Timothy O. Dickson, Yong Liu, et al.
IEEE Journal of Solid-State Circuits
Mihai Sanduleanu, Alberto Valdes-Garcia, et al.
CICC 2013