This paper discusses the design and implementation of a 94-GHz phased-array transceiver front-end in SiGe BiCMOS that is capable of receiving concurrently in both vertical (V) and horizontal (H) polarizations and time-duplexed transmission in either polarization. The compact front-end is implemented in 1.3 mm ×1.45 mm of silicon area to ensure compatibility with a scalable phased-array tile approach with λ/2 (∼1.6 mm spacing between elements. Each transceiver front-end includes variable transmitter (TX) and receiver (RX) gain and 360° variable phase shift in TX and RX. Co-integration of the transmit-receive (T/R) switch with the power amplifier (PA) and low-noise amplifier (LNA) matching network minimizes switch impact on RX noise figure (NF). A varactor-based passive reflection-type phase shifter (RTPS) is shared between the TX and RX to reduce area. Analysis of loss mechanisms in on-chip RTPS leads to a novel RTPS load that minimizes RTPS loss while ensuring that the amplitude variation across phase shift is <1 dB. In RX mode, the front-end achieves 30-dB RX gain, bandwidth of 15 GHz (84-99 GHz) with <10-dB NF in the high-gain mode. In TX mode, the front-end achieves < 2-dBm saturated output power and >0-dBm output-referred 1-dB compression point (OP1dB) in V and H polarizations (time-duplexed), 30-dB gain, and 8-GHz bandwidth (89-97 GHz). The 94-GHz phase shifters achieve full 360° variable phase shift with 5-bit phase resolution (11.25° resolution) and < 3° rms error and <1-dB rms gain error at 94 GHz. The front-end consumes 160 mW in RX mode for dual-polarization concurrent reception/phase-shifting and 116 mW in TX mode for time-duplexed V and H output in the-band.