Next Generation Infrared (IR) Laser Debonding / Silicon Handle Technology for Precision Chiplet Technology Applications
- Qianwen Chen
- Michael Belyansky
- et al.
- 2023
- ECTC 2023
Publications
Date
Featured collections
Popular topics
22 results for Michael Belyansky
Surface Energy Characterization for Die-Level Cu Hybrid Bonding
- Katsuyuki Sakuma
- Roy Yu
- et al.
- 2022
- ECTC 2022
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Blanket SMT with in situ N2 plasma treatment on the lang;100〉 wafer for the low-cost low-power technology application
- Jun Yuan
- Victor Chan
- et al.
- 2009
- IEEE Electron Device Letters
Overlay Performance in Permanent Bonded Wafer Integration Schemes
- Nathan Ip
- Michael Belyansky
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
A new technique for evaluating stacked nanosheet inner spacer TDDB reliability
- Tian Shen
- K. Watanabe
- et al.
- 2020
- IRPS 2020
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Atomic layer deposition of sidewall spacers: Process, equipment and integration challenges in state-of-the-art logic technologies
- Michael Belyansky
- Richard Conti
- et al.
- 2014
- ECS Meeting 2014