A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Publications
45 results for Matthew Ziegler
Layout-aware through-process circuit analysis
- Rama Singh
- Matt Ziegler
- et al.
- 2007
- DTIS 2007
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
Structured and tuned array generation (STAG) for high-performance random logic
- Matthew M. Ziegler
- Gary S. Ditlow
- et al.
- 2007
- GLSVLSI 2007
Multi-dimensional circuit and micro-architecture level optimization
- Qi Zhenyu
- Matthew Ziegler
- et al.
- 2007
- ISQED 2007