A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- Lukas Kull
- Danny Luu
- et al.
- 2017
- ISSCC 2017
Publications
This is our catalog of recent publications authored by IBM researchers, in collaboration with the global research community. We’re currently adding our back catalog of more than 110,000 publications. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.
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Year
51 results for Christian Menolfi
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- ISSCC 2017
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2015
- ISSCC 2015
A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2014
- ISSCC 2014
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
- Toke Meyer Andersen
- Florian Krismer
- et al.
- 2014
- ISSCC 2014
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- ISSCC 2013
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
- Gain Kim
- Marcel Kossel
- et al.
- 2020
- IEEE JSSC
A 24-72-GS/s 8-b time-interleaved SAR ADC with 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
- Lukas Kull
- Danny Luu
- et al.
- 2018
- IEEE JSSC