In today's microprocessors, external interrupts are the only processor resource that has no full virtualization hardware support. Therefore, they create significant overhead in the form of virtual machine (VM) context switches, especially in cloud and hyperscale datacenter systems, in which the physical processors are shared by a large number of virtual processors allocated to the VMs running on the system. The IBM POWER9 processor closes this gap in the processor hardware virtualization support by introducing an eXternal Interrupt Virtualization Engine (XIVE) architecture. XIVE defines a holistic interrupt delivery mechanism that supports multiple layers of interrupt coalescing and hardware-based routing of interrupts to the correct physical thread and target level. As required, individual interrupts can thus be routed directly to a user process, to a specific supervisor or an operating system, or to the hypervisor, thereby eliminating the need for interrupt rerouting in software and minimizing the number of context switches. In addition, XIVE provides the means to automatically trigger escalation interrupts to the next higher privilege level in case the target of an interrupt is not dispatched. In this paper, we discuss the fundamental concepts of the XIVE architecture and provide an overview of the XIVE-based interrupt controller implementation of the IBM POWER9 processor.