Wojciech Ozga, Patricia Sagmeister, et al.
CLOUD 2023
Network processors use highly parallel architectures to improve performance and reach multi-gigabit line-speeds. In this paper, we emulate a pipeline in a highly parallel nonprogrammable industrial InfiniBand Host Channel Adapter to make a performance and bottleneck analysis and, at the same time, explore the potential of a pipelined architecture. Therefore, starting from the original Host Channel Adapter model with multiple send- and receive-side packetprocessing units, we compare its performance capabilities with that of a pipelined design by introducing a central arbiter synchronizing the state machines of the different packet-processing instances to achieve a pipelined behavior. We show that the pipelined model achieves a performance comparable to that of the parallel design in most of our micro-benchmarks, making it a valid option for next-generation high-speed adapters. At the same time, our approach enables a deeper analysis of the original architecture and a better understanding of the actual processing requirements, and therefore offers valuable insights for future designs.
Wojciech Ozga, Patricia Sagmeister, et al.
CLOUD 2023
Jan Van Lunteren, Ronald Luijten, et al.
DATE 2019
Florian Auernhammer, R.L. Arndt
IBM J. Res. Dev
Samarjit Chakraborty, Simon Künzli, et al.
Computer Networks