Publication
IEEE TNANO
Paper

Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support

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Abstract

In this work, we propose valley-coupled spin-hall memories based on monolayer WSe2. The key features of the proposed memories are (a) the ability to switch magnets with perpendicular magnetic anisotropy and (b) an integrated gate that can modulate the charge/spin current (IC / IS) flow. The former attribute results in high energy efficiency (compared to the Giant-Spin Hall (GSH) effect-based devices with in-plane magnetic anisotropy magnets). The latter feature leads to a compact access-Transistor-less memory array design. We experimentally measure the gate controllability of the current as well as the non-local resistance associated with valley-coupled spin-hall effect. Based on the measured data, we develop a simulation framework to propose and analyze single-ended and differential valley-coupled spin-hall effect based magnetic memories (VSH-MRAM and DVSH-MRAM, respectively). At the array level, the proposed VSH/DVSH-MRAMs achieve 50%/11% lower write time, 59%/67% lower write energy, 12%/30% lower read time and 35%/41% lower read energy at iso-sense margin, compared to single-ended/differential Giant-Spin Hall (GSH/DGSH)-MRAMs. System level evaluation in the context of general-purpose processor and intermittently-powered system shows up to 3.14X and 1.98X better energy efficiency for the proposed (D)VSH-MRAMs over (D)GSH-MRAMs respectively. Further, the differential sensing of the proposed DVSH-MRAM leads to natural and simultaneous in-memory computation of bit-wise AND and NOR logic functions. Using this feature, we design a computation-in-memory (CiM) architecture that performs Boolean logic and addition with a single array access. System analysis performed by integrating our DVSH-MRAM: CiM in the Nios II processor shows up to 2.57X total energy savings, compared to DGSH-MRAM: CiM.

Date

01 Jan 2020

Publication

IEEE TNANO

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