Time-borrowing circuit designs and hardware prototyping for timing error resilience

Abstract

As dynamic variability increases with CMOS scaling, it is essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Three sequential circuit elements are described: TIMBER flip-flop, dedicated TIMBER flip-flop, and TIMBER latch. The TIMBER flip-flop uses two master latches and one slave latch to mask timing errors by borrowing discrete units of time from successive pipeline stages. It can be simplified to a dedicated TIMBER flip-flop that uses only two latches for time-borrowing (TB) at the expense of the flexibility of configuration as a conventional master-slave flip-flop. The TIMBER latch masks timing errors through continuous time-borrowing from successive pipeline stages, and supports runtime configuration as a conventional master-slave flip-flop. The TIMBER latch's continuous time-borrowing capability provides better time-borrowing capabilities at lower hardware cost, but the TIMBER flip-flop's discrete time-borrowing capability preserves the edge triggering property of a flip-flop, thus blocking the propagation of glitches and spurious transitions. In addition to evaluating the overhead and tradeoffs of TIMBER-based error masking on an industrial processor, the three circuits were also prototyped on an FPGA and their timing error masking capability was validated using a two-stage pipeline test structure. © 2014 IEEE.