Dynamically optimized synchronous communication for low power system on chip designs

Abstract

It is becoming necessary to have finer granularity and control of clock domains in System-on-Chip (SoC) designs for various reasons, power consumption being the primary consideration. In this work we have developed a mechanism to support frequency islands at the subsystem level. This paper describes a scheme for interconnecting and allowing synchronous communication between subsystems operating in different clock domains over a common synchronous bus interface. Our scheme provides a method to dynamically adjust the operating frequency of the source, target and the interconnecting bus during the synchronous communication while leaving other subsystems at their preferred operating frequencies. This scheme has a small overhead and results in significant power savings without a significant performance impact. When the bus utilization is less than 60%, our scheme results in an energy savings of 32-42%.