About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ICCD 1983
Conference paper
SYNTHESIS AND OPTIMIZATION OF MULTISTAGE LOGIC.
Abstract
An automatic synthesis system for Boolean networks is presented. The system transforms an arbitrary logical description into a set of interconnected circuits implementable in a given target technology. The algorithms are based on algebraic factorization and Boolean minimization. Two motions of Boolean division are employed. The procedure has been applied to many practical examples, including a 32-bit microprocessor and a computer ALU.