FAULT MODELLING AND SIMULATION OF SCVS CIRCUITS.

Abstract

The authors present an approach to the modeling and simulation of SCVS (single-ended cascode voltage switch) circuits, using a fault model that covers all single stuck-open and stuck-closed faults in the nMOS logic transistors as well as most of the single stuck-open faults in the precharge/buffer transistors. Simulation performance is enhanced by taking advantage of the structural properties of SCVS circuits, which separate them from more general MOS designs. These properties restrict the effects of transistor bidirectionality.