Wooram Lee, Caglar Ozdag, et al.
IEEE Journal of Solid-State Circuits
This letter presents symmetric vertical parallel plate (VPP) capacitors in 65-nm silicon-on-insulator CMOS technology. Three VPP capacitors with different metal layer options are examined with respect to effective capacitance density and Q-factor. An effective capacitance of 2.18 fF/ μm2 and a Q-factor of 23.2 at 1 GHz are obtained from a 1x + 2x (M1-M6) metal layer configuration's pre-de-embedding measurement. VPP capacitor symmetry, mismatch, leakage current density, vertical scalability, and variation characteristics from a 300-mm wafer are discussed. © 2007 IEEE.
Wooram Lee, Caglar Ozdag, et al.
IEEE Journal of Solid-State Circuits
Wooram Lee, Jean-Olivier Plouchart, et al.
IEEE JSSC
Neric Fong, Jean-Olivier Plouchart, et al.
VLSI Circuits 2002
Ongyeun Cho, Daeik Kim, et al.
DAC 2007