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Publication
IEEE Transactions on VLSI Systems
Paper
Speeding Up PEEC partial inductance computations using a QR-based algorithm
Abstract
The partial element equivalent circuit (PEEC) approach has been used in different forms for the computation of equivalent circuit elements for quasi-static and full-wave electromagnetic models. In this paper, we focus on the topic of large scale inductance computations. For many problems as part of PEEC modeling, partial inductances need to be computed to model interactions between a large numbers of objects. These computations can be very time and memory consuming. To date, several techniques have been devised to reduce the memory and time required to compute the partial inductance entities, as well as the time required to use them in a circuit analysis compute step. Some of the existing methods use hierarchical compression while some others are based on issues like properties of the inverse of the partial inductance matrix. However, because of inherent limitations, most of these methods are less suitable for PEEC applications. In this paper, we present an approach which is based on the compression of the partial inductance matrix utilizing the QR decomposition of the far coefficients submatrices. The QR-decomposed form is represented as a compressed SPICE-compatible circuit. This yields an efficient and mathematically consistent approach for reducing the storage and time requirements. © 2007 IEEE.