SOI: Opportunities and challenges for Sub-0.25 μu VLSI

Abstract

As VLSI minimum feature size is reduced into 0.25 μm regime and below, it is argued that utilization of SOI as the sub-strate offers a number of key advantages over bulk silicon. In the CMOS area, scaling of the room temperature CMOS is rapidly approaching its limits. In order to further improve bulk CMOS performance one has either to use SOI or to operate the CMOS at 77K. SOI devices in the 0.25 μm regime and below show significant performance improvement compared with bulk CMOS. This gives SOI the possibility of being used as substrate for the highest performance room temperature CMOS, provided a number of outstanding problems are solved. Ultimately to improve on 300K CMOS performance, one has to operate the CMOS at low temperature. SOI has a a clear advantage over bulk for low temperature (77K) operation at a reduced voltage as well. In bipolars, SOI allows realization of devices with no parasitic junction capacitance, sub-0.25 μm emitter widths, easy isolation, and CMOS-like density. Ease of isolation on SOI, allows easy integration of MOS and bipolar devices.