Simple and efficient CMOS circuit for fast VLSI adder realization

Abstract

A simple, yet efficient, scheme for a VLSI implementation of addition in CMOS is presented. The implementation of this scheme yields an adder with near minimal number of gates and a small and regular area that outperforms carry-lookahead and recurrence solver schemes. This is demonstrated by simulation of the actual implementation, using examples. The development of this scheme is based on a more realistic estimate of delay in VLSI-CMOS technology and careful selection of circuits than the estimates traditionally used. Using the proposed scheme developed, 32-bit addition in 14.2 ns was realized and, based on it, a 64-bit adder performing addtion in 16.0 ns was made possible.