TEST GENERATION FOR FET SWITCHING CIRCUITS.

Abstract

A method for computing test for failures of FET switching networks is described. A function-preserving, failure-preserving transformation of a switching network into a logic network is defined. There are efficient means for computing tests for failures in logic networks, specifically, the D-algorithm. Tests thus computed for the image logic network are automatically tests for failures in the original switching network. The logic network thus generated not only computes the same function; it also has the same failure-structure. Tests for the logic-network failures are computed by efficient test-generation procedures, using the D-algorithm. It is proven for the transformation that a test for a stuck failure in the logic network, is simultaneously a test for a short (or open) for the corresponding switch in the switching network. Run time for the transformation, from switching to logic network, increases linearly with the complexity of the switching network, so that its run time can be neglected.