ECTC 2005
Conference paper

Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver


The design, fabrication, assembly and characterization of a novel silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported. Electrical through-vias, high speed wiring and a through cavity for housing optoelectronic (OE) devices are critical features of the silicon carrier that allow high density integration of optical and electrical components on a single substrate, resulting in a small form factor system that is capable of meeting high bandwidth requirements of large computing systems. A novel hierarchical approach involving eutectic AuSn and SnPb solder systems and flip chip bonding technology is used to assemble the transceiver module. The optical system used for coupling light from the OE devices to waveguides is based on a relay lens that is integrated into the OE array. The measurement and model for alignment tolerance analysis showed constant coupling efficiency from the OE to waveguide over a range of ±10 μm, giving an excellent margin for alignment. Electrical simulations and measurement of silicon carrier through-vias showed an insertion loss of better than l dB at 20 GHz. Simulations and measurements also exhibited an attenuation of 4.3 dB/cm at 20 GHz for high speed wiring on the silicon carrier, which was adequate for 20 Gbps data transmission over a channel length of 7 mm. © 2005 IEEE.