Series Resistance Reduction with Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET

Abstract

Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependent drain current. This paper encompasses: 1) extensive investigation of the impact of series resistance on IM, JL mode, and JLAM NWFET architectures; 2) a proposed approach to mitigate the series resistance; and 3) linearity assessment of stacked JLAM-NWFET for radio frequency (RF) applications. We have suggested that by decreasing the channel doping in the bottom NW with respect to the top NW in a stack, the current can be significantly improved along with the reduction in series resistance. This improves the overall uniformity of drain current in each NW for stacked JLAM-NWFET. The linearity performance of the device is assessed in terms of following figure of merits (FOMs): IIP3, 1-dB compression point, and higher order derivative of transconductance g m 2 and g m 3. These FOMs are evaluated through numerical simulations using Sentaurus Technology Computer-Aided Design to confirm the robustness of the device against intermodulation distortion making it suitable for low power radio frequency integrated circuit design applications. The proposed solution allows higher drive current, improved linearity, and thus lower distortion in stacked JLAM-NWFET.